EV4101【PDF 5/68 页】32-bit Microprocessor that Executes MIPS

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TinyRISC

EV4101 Microprocessor Reference Device Technical Summary

1 Introduction

The TinyRISC EV4101 Microprocessor Reference Device is a single chip

implementation of the TinyRISC TR4101 Microprocessor, a component

of LSI Logic’s CoreWare

Library. The EV4101 Reference Device design

contains an extended bus controller (XC) module and several building

blocks: instruction and data caches, a timer, a multiply divide unit (MDU),

and a basic bus interface unit and cache controller (BBCC). The EV4101

also includes a hardware debug (DBX) module and SerialICE port to

enable the user to debug and download software applications through

the SerialICE concept. The EV4101 is a 32-bit microprocessor that

executes MIPS I, a subset of MIPS II, and a subset of the MIPS16

instructions. MIPS16 is a 16-bit wide instruction set that greatly reduces

code size and thereby the amount of memory needed. Figure 1 is a block

diagram of the EV4101 Reference Device.

Figure 1

EV4101 Reference Device Block Diagram

TR4101

Microprocessor

Core

FlexLink

Interface

CBus

I-Cache

Set 1

Debug

Module

(DBX)

Timer 0

Bus

Controller

(XC)

BBus

Extended

BIU and

Cache

Controller

(BBCC)

PCI-like

Memory

Interface

I-Cache

Set 0

D-Cache

Multiply/

Divide Unit

(MDU)

Timer 1

Rx Input

Serial Clock

Tx Output

Rx Interrupt

SerialICE

Port

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